View HPCL7800_836165.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

H
High CMR Isolation Amplifiers Technical Data
HCPL-7800 HCPL-7800A HCPL-7800B
Features
* 15 kV/s Common-Mode Rejection at VCM = 1000 V* * Compact, Auto-Insertable Standard 8-pin DIP Package * 4.6 V/C Offset Drift vs. Temperature * 0.9 mV Input Offset Voltage * 85 kHz Bandwidth * 0.1% Nonlinearity * Worldwide Safety Approval: UL 1577 (3750 V rms/1 min), VDE 0884 and CSA * Advanced Sigma-Delta () A/D Converter Technology * Fully Differential Circuit Topology * 1 m CMOS IC Technology
* Switch-Mode Power Supply Signal Isolation * General Purpose Analog Signal Isolation * Transducer Isolation
Description
The HCPL-7800 high CMR isolation amplifier provides a unique combination of features ideally suited for motor control circuit designers. The product provides the precision and stability needed to accurately monitor motor current in highnoise motor control environments, providing for smoother control (less "torque ripple") in various types of motor control applications. This product paves the way for a smaller, lighter, easier to produce, high noise rejection, low cost solution to motor current sensing. The product can also be used for general analog signal isolation applications requiring high accuracy, stability and linearity under similarly severe noise conditions. For general
applications, we recommend the HCPL-7800 which exhibits a part-to-part gain tolerance of 5%. For precision applications, HP offers the HCPL-7800A and HCPL-7800B, each with part-topart gain tolerances of 1%. The HCPL-7800 utilizes sigmadelta () analog-to-digital converter technology, chopper stabilized amplifiers, and a fully differential circuit topology fabricated using HP's 1 m CMOS IC process. The part also couples our high-efficiency, highspeed AlGaAs LED to a highspeed, noise-shielded detector
Applications
* Motor Phase Current Sensing * General Purpose Current Sensing * High-Voltage Power Source Voltage Monitoring
*The terms common-mode rejection (CMR) and isolation-mode rejection (IMR) are used interchangeably throughout this data sheet.
Functional Diagram
V DD1 1 I DD1 I DD2 8 V DD2
V IN+
2
I IN + +
IO
7
V OUT+
V IN-
3
-
-
6
V OUT-
GND1
4
5 GND2
CMR SHIELD
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
1-216
5965-3592E
using our patented "light-pipe" optocoupler packaging technology. Together, these features deliver unequaled isolation-mode noise
rejection, as well as excellent offset and gain accuracy and stability over time and temperature. This performance is delivered in a compact, autoinsertable, industry standard 8-
pin DIP package that meets worldwide regulatory safety standards (gull-wing surface mount option #300 also available).
Ordering Information:
HCPL-7800x No Specifier = 5% Gain Tol.; Mean Gain Value = 8.00 A = 1% Gain Tol.; Mean Gain Value = 7.93 B = 1% Gain Tol.; Mean Gain Value = 8.07 Option yyy 300 = Gull Wing Surface Mount Lead Option 500 = Tape/Reel Package Option (1 k min.) Option datasheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information.
Package Outline Drawings
Standard DIP Package
9.40 (0.370) 9.90 (0.390) 8 7 6 5
TYPE NUMBER* DATE CODE 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310)
0.20 (0.008) 0.33 (0.013)
HP 7800 YYWW PIN ONE 1.19 (0.047) MAX. 1 2 3 4
5 TYP.
1.78 (0.070) MAX.
4.70 (0.185) MAX. PIN ONE 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1 2 3 0.76 (0.030) 1.24 (0.049) 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) DIMENSIONS IN MILLIMETERS AND (INCHES). 4
PIN DIAGRAM VDD1 VIN+ VIN- VDD2 8 VOUT+ 7 VOUT- 6
GND1 GND2 5
* TYPE NUMBER FOR: HCPL-7800 = 7800 HCPL-7800A = 7800A HCPL-7800B = 7800B
1-217
OPTOCOUPLERS
Gull Wing Surface Mount Option 300*
PIN LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
1.02 (0.040) 1.19 (0.047)
4.83 TYP. (0.190) HP 7800 YYWW 6.350 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010)
MOLDED
1
2
3
4
1.19 (0.047) 1.78 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.380 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
0.20 (0.008) 0.33 (0.013)
1.080 0.320 (0.043 0.013) 2.540 (0.100) BSC
0.51 0.130 (0.020 0.005)
0.635 0.25 (0.025 0.010) 12 NOM.
DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 * REFER TO OPTION 300 DATA SHEET FOR MORE INFORMATION.
LEAD COPLANARITY MAXIMUM: 0.102 (0.004)
Maximum Solder Reflow Thermal Profile
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 T = 145C, 1C/SEC T = 115C, 0.3C/SEC
TEMPERATURE - C
T = 100C, 1.5C/SEC
1
2
3
4
5
6
7
8
9
10
11
12
TIME - MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
1-218
The HCPL-7800 has been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. VDE Approved according to VDE 0884/06.92.
Insulation and Safety Related Specifications
Parameter Min. External Air Gap (External Clearance) Min. External Tracking Path (External Creepage) Min. Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(IO1) L(IO2) Value Units 7.4 mm 8.0 0.5 mm mm Conditions Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity DIN IEC 112/VDE 0303 Part 1
CTI
175
V
III a
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
VDE 0884 (06.92) Insulation Characteristics
Description Installation classification per DIN VDE 0110, Table 1 for rated mains voltage 300 V rms for rated mains voltage 600 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1)* Maximum Working Insulation Voltage Input to Output Test Voltage, Method b** VPR = 1.875 x VIORM, Production test with tp = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a** VPR = 1.5 x VIORM, Type and sample test with tp = 60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage** (Transient Overvoltage tTR = 10 sec) Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure 27) Case Temperature Input Power Output Power Insulation Resistance at TS, VIO = 500 V Symbol Characteristic I-IV I-III 40/100/21 2 848 1591 Unit
VIORM VPR
V peak V peak
VPR
1273
V peak
VTR
6000
V peak C mW mW
TS PS,Input PS,Output RS
175 80 250 1x1012
*This part may also be used in Pollution Degree 3 environments where the rated mains voltage is 300 V rms (per DIN VDE 0110). **Refer to the front of the optocoupler section of the current catalog for a more detailed description of VDE 0884 and other product safety requirements. Note: Optocouplers providing safe electrical separation per VDE 0884 do so only within the safety-limiting values to which they are qualified. Protective cut-out switches must be used to ensure that the safety limits are not exceeded.
1-219
OPTOCOUPLERS
Regulatory Information
Absolute Maximum Ratings
Parameter Storage Temperature Ambient Operating Temperature Supply Voltages Steady-State Input Voltage Two Second Transient Input Voltage Output Voltages Lead Solder Temperature (1.6 mm below seating plane, 10 sec.) Reflow Temperature Profile Symbol TS TA VDD1, VDD2 VIN+, VINVOUT+, VOUTTLS Min. -55 - 40 0.0 -2.0 -6.0 -0.5 Max. 125 100 5.5 VDD1 +0.5 VDD2 +0.5 260 Unit C C V V V C Note
1
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter Ambient Operating Temperature Supply Voltages Input Voltage Output Current Symbol TA VDD1, VDD2 VIN+, VIN|IO| Min. -40 4.5 -200 Max. 85 5.5 200 1 Unit C V mV mA Note 2 3 4 5
1-220
DC Electrical Specifications
All specifications and figures are at the nominal operating condition of VIN+ = 0 V, VIN- = 0 V, TA = 25C, VDD1 = 5.0 V, and VDD2 = 5.0 V, unless otherwise noted.
Parameter Input Offset Voltage Input Offset Drift vs. Temperature Abs. Value of Input Offset Drift vs. Temperature Input Offset Drift vs. VDD1 Input Offset Drift vs. VDD2 Gain ( 5% Tol.) Gain - A Version ( 1% Tol.) Gain - B Version ( 1% Tol.) Gain Drift vs. Temperature Abs. Value of Gain Drift vs. Temperature Gain Drift vs. VDD1 Gain Drift vs. VDD2 200 mV Nonlinearity 200 mV Nonlinearity Drift vs. Temperature 200 mV Nonlinearity Drift vs. VDD1 200 mV Nonlinearity Drift vs. VDD2 100 mV Nonlinearity Maximum Input Voltage Before Output Clipping Average Input Bias Current Input Bias Current Temperature Coefficient Average Input Resistance Input Resistance Temperature Coefficient Input DC Common-Mode Rejection Ratio Output Resistance Output Resistance Temperature Coefficient Output Low Voltage Output High Voltage Output Common-Mode Voltage Input Supply Current Output Supply Current Symbol VOS dVOS/dT |dVOS/dT| dVOS/dVDD1 dVOS/dVDD2 G GA GB dG/dT |dG/dT| dG/dVDD1 dG/dVDD2 NL200 dNL200/dT dNL200/dVDD1 dNL200/dVDD2 NL100 |VIN+|max IIN dIIN/dT RIN dRIN/dT CMRRIN RO dRO/dT VOL VOH VOCM IDD1 IDD2 Min. -1.8 Typ. -0.9 -2.1 4.6 30 -40 8.00 7.93 8.07 0.001 0.001 Max. 0.0 Unit mV V/C V/C V/V V/V 8.40 8.01 8.15 %/C %/C %/V %/V % % pts/C % pts/V % pts/V 0.25 % mV nA nA/C k %/C dB %/C V V V mA mA |VIN+| = 500 mV IOUT+ = 0 A, IOUT- = 0 A -40C < TA < 85C 4.5 V < VDD1 < 5.5 V VIN+ = 200 mV, -40C < TA < 85C 4.5 V < VDD2 < 5.5 V VOUT = 0 V or VDD2 14 14 17 18 23 24 -200 mV < VIN+ < 200 mV Test Conditions Fig. 1 1, 2 1 1, 3 1, 4 1, 5 Note 6 7 8 9 10
7.61 7.85 7.99
5, 6 5 5, 7 5, 8 5, 9 5, 10 5, 11 5, 12 -100 mV< VIN+ < 100 mV 5, 13 14 15, 16
11 12 13 14 15 16 17 18 19
0.21 -0.06 0.2 0.35 -0.001 -0.005 -0.007 0.1 300 -670 3 530 0.38 72 11 0.6 1.18 3.61 2.39 10.7 11.6
20
15
20
21 5
22
2.20
2.60 15.5 14.5
Output Short-Circuit Current
|IOSC|
9.3
mA
25
1-221
OPTOCOUPLERS
AC Electrical Specifications
All specifications and figures are at the nominal operating condition of VIN+ = 0 V, VIN- = 0 V, TA = 25C, VDD1 = 5.0 V, and VDD2 = 5.0 V, unless otherwise noted.
Parameter Rising Edge Isolation Mode Rejection Falling Edge Isolation Mode Rejection Isolation Mode Rejection Ratio at 60 Hz Propagation Delay to 10% Propagation Delay to 50% Propagation Delay to 90% Rise/Fall Time (10%-90%) Bandwidth (-3 dB) Bandwidth (-45) RMS Input-Referred Noise Power Supply Rejection Symbol IMRR IMRF IMRR tPD10 tPD50 tPD90 tR/F f-3dB f-45 VN PSR 50 Min. 10 10 Typ. 25 15 >140 2.0 3.4 6.3 4.3 85 35 300 5 3.3 5.6 9.9 6.6 Max. Unit kV/s kV/s dB s s s s kHz kHz V rms mVp-p Bandwidth = 100 kHz 25, 26 28 29 23, 24 -40C < TA < 85C 19 21, 22 27 Test Conditions VIM = 1 kV Fig. 19, 20 Note 26
Package Characteristics
All specifications and figures are at the nominal operating condition of VIN+ = 0 V, VIN- = 0 V, TA = 25C, VDD1 = 5.0 V, and VDD2 = 5.0 V, unless otherwise noted.
Parameter Input-Output Momentary Withstand Voltage* Input-Output Resistance Symbol VISO RI-O Min. 3750 1012 1011 Input-Output Capacitance Input IC Junction-toCase Thermal Resistance Output IC Junction-to-Case Thermal Resistance CI-O jci jco 0.7 96 114 pF C/W C/W 1013 Typ. Max. Unit V rms Test Conditions t = 1 min., RH 50% TA = 25C TA = 100C f = 1 MHz 30 32 VI-O = 500 Vdc Fig. Note 30, 31 30
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification, or HP Application Note 1074, "Optocoupler Input-Output Endurance Voltage."
1-222
Notes: General Note: Typical values represent the mean value of all characterization units at the nominal operating conditions. Typical drift specifications are determined by calculating the rate of change of the specified parameter versus the drift parameter (at nominal operating conditions) for each characterization unit, and then averaging the individual unit rates. The corresponding drift figures are normalized to the nominal operating conditions and show how much drift occurs as the particular drift parameter is varied from its nominal value, with all other parameters held at their nominal operating values. Figures show the mean drift of all characterization units as a group, as well as the 2-sigma statistical limits. Note that the typical drift specifications in the tables below may differ from the slopes of the mean curves shown in the corresponding figures. 1. HP recommends the use of nonchlorine activated fluxes. 2. The HCPL-7800 will operate properly at ambient temperatures up to 100C but may not meet published specifications under these conditions. 3. DC performance can be best maintained by keeping VDD1 and VDD2 as close as possible to 5 V. See application section for circuit recommendations. 4. HP recommends operation with VIN= 0 V (tied to GND1). Limiting VIN+ to 100 mV will improve DC nonlinearity and nonlinearity drift. If VIN- is brought above 800 mV with respect to GND1, an internal test mode may be activated. This test mode is not intended for customer use. 5. Although, statistically, the average difference in the output resistance of pins 6 and 7 is near zero, the standard deviation of the difference is 1.3 due to normal process variations. Consequently, keeping the output current below 1 mA will ensure the best offset performance. 6. Data sheet value is the average change in offset voltage versus temperature at TA = 25C, with all other parameters held constant. This value is expressed as the change in offset voltage per C change in temperature. 7. Data sheet value is the average magnitude of the change in offset voltage versus temperature at TA = 25C, with all other parameters held constant. This value is expressed
as the change in magnitude per C change in temperature. 8. Data sheet value is the average change in offset voltage versus input supply voltage at VDD1 = 5 V, with all other parameters held constant. This value is expressed as the change in offset voltage per volt change of the input supply voltage. 9. Data sheet value is the average change in offset voltage versus output supply voltage at VDD2 = 5 V, with all other parameters held constant. This value is expressed as the change in offset voltage per volt change of the output supply voltage. 10. Gain is defined as the slope of the best-fit line of differential output voltage (VOUT+ - VOUT-) versus differential input voltage (VIN+ -VIN-) over the specified input range. 11. Data sheet value is the average change in gain versus temperature at TA = 25C, with all other parameters held constant. This value is expressed as the percentage change in gain per C change in temperature. 12. Data sheet value is the average magnitude of the change in gain versus temperature at TA = 25C, with all other parameters held constant. This value is expressed as the percentage change in magnitude per C change in temperature. 13. Data sheet value is the average change in gain versus input supply voltage at VDD1 = 5 V, with all other parameters held constant. This value is expressed as the percentage change in gain per volt change of the input supply voltage. 14. Data sheet value is the average change in gain versus output supply voltage at VDD2 = 5 V, with all other parameters held constant. This value is expressed as the percentage change in gain per volt change of the output supply voltage. 15. Nonlinearity is defined as the maximum deviation of the output voltage from the best-fit gain line (see Note 10), expressed as a percentage of the full-scale differential output voltage range. For example, an input range of 200 mV generates a full-scale differential output range of 3.2 V ( 1.6 V); a maximum output deviation of 6.4 mV would therefore correspond to a nonlinearity of 0.2%.
16. Data sheet value is the average change in nonlinearity versus temperature at TA = 25C, with all other parameters held constant. This value is expressed as the number of percentage points that the nonlinearity will change per C change in temperature. For example, if the temperature is increased from 25C to 35C, the nonlinearity typically will decrease by 0.01 percentage points (10C times -0.001 % pts/C) from 0.2% to 0.19%. 17. Data sheet value is the average change in nonlinearity versus input supply voltage at VDD1 = 5 V, with all other parameters held constant. This value is expressed as the number of percentage points that the nonlinearity will change per volt change of the input supply voltage. 18. Data sheet value is the average change in nonlinearity versus output supply voltage at VDD2 = 5 V, with all other parameters held constant. This value is expressed as the number of percentage points that the nonlinearity will change per volt change of the output supply voltage. 19. NL100 is the nonlinearity specified over an input voltage range of 100 mV. 20. Because of the switched-capacitor nature of the input sigma-delta converter, time-averaged values are shown. 21. This parameter is defined as the ratio of the differential signal gain (signal applied differentially between pins 2 and 3) to the common-mode gain (input pins tied together and the signal applied to both inputs at the same time), expressed in dB. 22. When the differential input signal exceeds approximately 300 mV, the outputs will limit at the typical values shown. 23. The maximum specified input supply current occurs when the differential input voltage (VIN+ - VIN-) = 0 V. The input supply current decreases approximately 1.3 mA per 1 V decrease in VDD1. 24. The maximum specified output supply current occurs when the differential input voltage (VIN+ - VIN-) = 200 mV, the maximum recommended operating input voltage. However, the output supply current will continue to rise for differential input voltages up to approximately 300 mV, beyond which the output supply current remains constant.
1-223
OPTOCOUPLERS
25. Short circuit current is the amount of output current generated when either output is shorted to VDD2 or ground. 26. IMR (also known as CMR or Common Mode Rejection) specifies the minimum rate of rise of an isolation mode noise signal at which small output perturbations begin to appear. These output perturbations can occur with both the rising and falling edges of the isolation-mode wave form and may be of either polarity. When the perturbations first appear, they occur only occasionally and with relatively small peak amplitudes (typically 20-30 mV at the output of the recommended application circuit). As the magnitude of the isolation mode transients increase, the regularity and amplitude of the perturbations also increase. See applications section for more information. 27. IMRR is defined as the ratio of differential signal gain (signal applied differentially between pins 2 and 3) to
the isolation mode gain (input pins tied to pin 4 and the signal applied between the input and the output of the isolation amplifier) at 60 Hz, expressed in dB. 28. Output noise comes from two primary sources: chopper noise and sigmadelta quantization noise. Chopper noise results from chopper stabilization of the output op-amps. It occurs at a specific frequency (typically 200 kHz at room temperature), and is not attenuated by the internal output filter. A filter circuit can be easily added to the external post-amplifier to reduce the total rms output noise. The internal output filter does eliminate most, but not all, of the sigma-delta quantization noise. The magnitude of the output quantization noise is very small at lower frequencies (below 10 kHz) and increases with increasing frequency. See applications section for more information.
29. Data sheet value is the differential amplitude of the transient at the output of the HCPL-7800 when a 1 Vpk-pk, 1 MHz square wave with 5 ns rise and fall times is applied to both VDD1 and VDD2. 30. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together. 31. In accordance with UL1577, for devices with minimum VISO specified at 3750 Vrms, each optocoupler is prooftested by applying an insulation test voltage greater-than-or-equal-to 4500 Vrms for one second (leak current detection limit, II-O < 5 A). This test is performed before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table. 32. Case temperature was measured with a thermocouple located in the center of the underside of the package.
dVOS - INPUT-REFERRED OFFSET DRIFT - V
1500 MEAN 2 SIGMA 1000
+5 V
+5 V
+15 V 0.1 F
0.1 F 1 2 3 4
HCPL-7800 8 7 6 5
0.1 F 10 K + 10 K AD624CD GAIN = 1000 V OUT
500
0
-500
0.33 F
0.33 F
0.1 F
-1000 -40
-20
0
20
40
60
80
100
-15 V
TA - TEMPERATURE - C
Figure 1. Input Offset Voltage Test Circuit.
Figure 2. Input-Referred Offset Drift vs. Temperature.
1-224
dVOS - INPUT-REFERRED OFFSET DRIFT - V
600 MEAN 2 SIGMA 400
dVOS - INPUT-REFERRED OFFSET DRIFT - V
400 MEAN 2 SIGMA 300
200
200
0 -200 -400
100
0 -100
-600 4.4
4.6
4.8
5.0
5.2
5.4
5.6
-200 4.4
4.6
4.8
5.0
5.2
5.4
5.6
VDD1 - INPUT SUPPLY VOLTAGE - V
VDD2 - OUTPUT SUPPLY VOLTAGE - V
Figure 3. Input-Referred Offset Drift vs. VDD1 (VDD2 = 5 V).
Figure 4. Input-Referred Offset Drift vs. VDD2 (VDD1 = 5 V).
1.5
+5 V
+5 V
+15 V
1.0
MEAN 2 SIGMA
0.1 F 1 V IN 2 3 0.01 F 4
HCPL-7800 8 7 6 5
0.1 F 10 K + 10 K AD624CD GAIN = 1 V OUT
dG - GAIN DRIFT- %
0.1 F
0.5
0
-0.5
0.33 F
0.33 F
0.1 F
-1.0 -40
-20
0
20
40
60
80
100
-15 V
T A - TEMPERATURE - C
Figure 5. Gain and Nonlinearity Test Circuit.
Figure 6. Gain Drift vs. Temperature.
0.5
0.5 MEAN 2 SIGMA
0.3 MEAN 2 SIGMA
ERROR - % OF FULL-SCALE
0
dG - GAIN DRIFT- %
dG - GAIN DRIFT- %
0.4
0.2
0.3
0.1
-0.5
0.2
0
-1.0
0.1
-0.1
-1.5 MEAN 2 SIGMA -2.0 4.4 4.6 4.8 5.0 5.2 5.4 5.6
0 -0.1 4.4 4.6 4.8 5.0 5.2 5.4 5.6
-0.2 -0.3 -0.2
-0.1
0
0.1
0.2
V DD1 - INPUT SUPPLY VOLTAGE - V
V DD2 - OUTPUT SUPPLY VOLTAGE - V
V IN - INPUT VOLTAGE - V
Figure 7. Gain Drift vs. VDD1 (VDD2 = 5 V).
Figure 8. Gain Drift vs. VDD2 (VDD1 = 5 V).
Figure 9. 200 mV Nonlinearity Error Plot.
1-225
OPTOCOUPLERS
dNL 200 - 200 mV NON-LINEARITY DRIFT - % PTS
dNL 200 - 200 mV NON-LINEARITY DRIFT - % PTS
dNL 200 - 200 mV NON-LINEARITY DRIFT - % PTS
0.15 MEAN 2 SIGMA 0.10
0.06 MEAN 2 SIGMA
0.06 MEAN 2 SIGMA 0.04
0.04
0.02
0.05
0.02
0
0
0
-0.02 -0.04 -0.06 4.4 4.6 4.8 5.0 5.2 5.4 5.6 V DD1 - INPUT SUPPLY VOLTAGE - V
-0.05
-0.02
-0.10 -40
-0.04 4.4 4.6 4.8 5.0 5.2 5.4 5.6 V DD2 - OUTPUT SUPPLY VOLTAGE - V
-20
0
20
40
60
80
100
TA - TEMPERATURE - C
Figure 10. 200 mV Nonlinearity Drift vs. Temperature.
Figure 11. 200 mV Nonlinearity Drift vs. VDD1 (VDD2 = 5 V).
Figure 12. 200 mV Nonlinearity Drift vs. VDD2 (VDD1 = 5 V).
0.15 0.10
ERROR - % OF FULL-SCALE
4.0
0 -200
IIN - INPUT CURRENT - nA
3.5
VO - OUTPUT VOLTAGE - V
0.05 0 -0.05 -0.10 -0.15 -0.20 -0.10
3.0
POSITIVE OUTPUT (PIN 7) NEGATIVE OUTPUT (PIN 6)
-400
2.5
-600
2.0
-800
1.5 1.0
-1000 -1200
MEAN 2 SIGMA -0.05 0 0.05 0.10
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
-0.2
-0.1
0
0.1
0.2
V IN - INPUT VOLTAGE - V
V IN - INPUT VOLTAGE - V
V IN - INPUT VOLTAGE - V
Figure 13. 100 mV Nonlinearity Error Plot.
Figure 14. Typical Output Voltages vs. Input Voltage.
Figure 15. Typical Input Current vs. Input Voltage.
2
10.5
I DD2 - OUTPUT SUPPLY CURRENT - mA
12.0 TA = 85C TA = 25C TA = -40C 11.5
I IN - INPUT CURRENT - mA
0 -2
I DD1 - INPUT SUPPLY CURRENT - mA
10.0
-4
9.5
11.0
-6
9.0 TA = -40C TA = 25C TA = 85C 8.5 -0.4 -0.3 -0.2 -0.1 V
IN
10.5
-8 -10 -6 -4 -2 0 2 4 6 V IN - INPUT VOLTAGE - V
0
0.1
0.2
0.3
0.4
10.0 -0.4 -0.3 -0.2 -0.1
0
0.1
0.2
0.3
0.4
- INPUT VOLTAGE - V
V IN - INPUT VOLTAGE - V
Figure 16. Typical Input Current vs. Input Voltage.
Figure 17. Typical Input Supply Current vs. Input Voltage.
Figure 18. Typical Output Supply Current vs. Input Voltage.
1-226
330 pF
5.11 K
+5 V
+15 V 0.1 F
78L05 IN OUT 1 2 9V 0.1 F 0.1 F 3 4
HCPL-7800 8 7 6 5
0.1 F 1.00 K + 1.00 K OP-42 VOUT
0.1 F 330 pF PULSE GEN. + V IM 5.11 K -15 V
Figure 19. Isolation Mode Rejection Test Circuit.
10 DELAY TO 90% RISE/FALL TIME DELAY TO 50% DELAY TO 10%
8
1000 V
t - TIME - s
6
V IM
0V
4
50 mV PERTURBATION (DEFINITION OF FAILURE)
2
VO
0V
0 -40
-20
0
20
40
60
80
100
TA - TEMPERATURE - C
Figure 20. Typical IMR Failure Waveform.
Figure 21. Typical Propagation Delays and Rise/Fall Time vs. Temperature.
1-227
OPTOCOUPLERS
V IN
50%
t PD90 t PD50 t PD10
90% V OUT 10% 50%
t R/F
10.0 K
+5 V
+5 V
+15 V 0.1 F
0.1 F 1 V IN 2 3 0.01 F 4
HCPL-7800 8 7 6 5
0.1 F 2.00 K + 2.00 K OP-42 V OUT
0.1 F 10.0 K -15 V
Figure 22. Propagation Delay and Rise/Fall Time Test Circuit.
f -45 - 45 DEGREE PHASE BANDWIDTH - kHz
0
0 -5
f -3 dB - 3 dB BANDWIDTH - kHz
110 3 dB BANDWIDTH 45 DEGREE PHASE BANDWIDTH
48
3.0
V N - RMS INPUT-REFERRED NOISE - mV
-10
2.5
RELATIVE AMPLITUDE - dB
-1
-15
100
44
NO BANDWIDTH LIMITING BANDWIDTH LIMITED TO 100 kHz BANDWIDTH LIMITED TO 10 kHz
O - PHASE - DEGREES
2.0
90
40
-2
-30
1.5
80
36
1.0
-3 AMPLITUDE PHASE -4 100 500 1000 5000 10000
-45
70
32
0.5 0 0 50 100 150 200 250 V IN - INPUT VOLTAGE - mV
-60 50000 100000
60 -40
-20
0
20
40
60
80
28 100
f - FREQUENCY - Hz
T A - TEMPERATURE - C
Figure 23. Typical Amplitude and Phase Response vs. Frequency.
Figure 24. Typical 3 dB and 45 Bandwidths vs. Temperature.
Figure 25. Typical RMS Input-Referred Noise vs. Input Voltage.
1-228
FLOATING POSITIVE SUPPLY HV+ GATE DRIVE CIRCUIT R3 10.0 K +5 V IN U1 78L05 OUT C2 0.1 F R5 39 + C3 0.01 F 1 2 MOTOR R SENSE C6 75 pF 3 4 8 7 U2 HCPL-7800 6 5 C4 0.1 F +15 V C8 0.1 F R1 2.00 K U3 + R2 2.00 K C7 0.1 F R4 10.0 K -15 V HVMC34081 V OUT C5 75 pF
C1 0.1 F
Figure 26. Recommended Application Circuit.
400 OUTPUT POWER, PS INPUT POWER, PS
PS - POWER - mW
300
200
100
0
0
20 40 60 80 100 120 140 160 180 175 TA - TEMPERATURE - C
Figure 27. Dependence of SafetyLimiting Parameters on Ambient Temperature.
Applications Information
Functional Description Figure 28 shows the primary functional blocks of the HCPL7800. In operation, the sigmadelta analog-to-digital converter converts the analog input signal into a high-speed serial bit stream, the time average of which is directly proportional to the input signal. This high speed stream of digital data is encoded and optically transmitted to the detector circuit. The detected
signal is decoded and converted into accurate analog voltage levels, which are then filtered to produce the final output signal. To help maintain device accuracy over time and temperature, internal amplifiers are chopperstabilized. Additionally, the encoder circuit eliminates the effects of pulse-width distortion of the optically transmitted data by generating one pulse for every edge (both rising and falling) of
the converter data to be transmitted, essentially converting the widths of the sigma-delta output pulses into the positions of the encoder output pulses. A significant benefit of this coding scheme is that any non-ideal characteristics of the LED (such as non-linearity and drift over time and temperature) have little, if any, effect on the performance of the HCPL-7800.
1-229
OPTOCOUPLERS
Circuit Information The recommended application circuit is shown in Figure 26. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple three-terminal voltage regulator. The input of the HCPL-7800 is connected directly to the current sensing resistor. The differential output of the isolation amplifier is converted to a ground-referenced single-ended output voltage with a simple differential amplifier circuit. Although the application circuit is relatively simple, a few general recommendations should be followed to ensure optimal performance. As shown in Figure 26, 0.1 F bypass capacitors should be located as close as possible to the input and output power supply pins of the HCPL-7800. Notice that pin 2 (VIN+) is bypassed with a 0.01 F capacitor to reduce input offset voltage that can be caused by the combination of long input leads and the switchedcapacitor nature of the input circuit. With pin 3 (VIN-) tied directly to pin 4 (GND1), the power-supply return line also functions as the sense line for the negative side of the current-sensing resistor; this allows a single twisted pair of wire to connect the isolation amplifier to the sense resistor. In some applications, however, better performance may be obtained by connecting pins 2 and 3 (VIN+ and VIN-) directly across the sense resistor with twisted pair wire and using a separate wire for the power supply return line. Both input pins should be bypassed with 0.01
F capacitors close to the isolation amplifier. In either case, it is recommended that twistedpair wire be used to connect the isolation amplifier to the currentsensing resistor to minimize electro-magnetic interference of the sense signal. To obtain optimal CMR performance, the layout of the printed circuit board (PCB) should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground plane on the PCB does not pass directly below the HCPL7800. An example single-sided PCB layout for the recommended application circuit is shown in Figure 29. The trace pattern is shown in "X-ray" view as it would be seen from the top of the PCB; a mirror image of this layout can be used to generate a PCB. An inexpensive 78L05 threeterminal regulator is shown in the recommended application circuit. Because the performance of the isolation amplifier can be affected by changes in the power supply voltages, using regulators with tighter output voltage tolerances will result in better overall circuit performance. Many different regulators that provide tighter output voltage tolerances than the 78L05 can be used, including: TL780-05 (Texas Instruments), LM340LAZ-5.0 and LP2950CZ5.0 (National Semiconductor). The op-amp used in the external post-amplifier circuit should be of sufficiently high precision so that it does not contribute a significant amount of offset or offset drift relative to the contribution from the isolation amplifier. Generally, op-amps with bipolar input stages
exhibit better offset performance than op-amps with JFET or MOSFET input stages. In addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely affect the response speed of the overall circuit. The post-amplifier circuit includes a pair of capacitors (C5 and C6) that form a single-pole low-pass filter; these capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier. Many different op-amps could be used in the circuit, including: MC34082A (Motorola), TL032A, TLO52A, and TLC277 (Texas Instruments), LF412A (National Semiconductor). The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate CMRR and adequate gain tolerance for the overall circuit. Resistor networks can be used that have much better ratio tolerances than can be achieved using discrete resistors. A resistor network also reduces the total number of components for the circuit as well as the required board space. The current-sensing resistor should have a relatively low value of resistance to minimize power dissipation, a fairly low inductance to accurately reflect high-frequency signal components, and a reasonably tight tolerance to maintain overall circuit accuracy. Although decreasing the value of the sense resistor decreases power dissipation, it also decreases the full-scale input voltage making iso-amp offset voltage effects more significant. These two
1-230
conflicting considerations, therefore, must be weighed against each other in selecting an appropriate sense resistor for a particular application. To maintain circuit accuracy, it is recommended that the sense resistor and the isolation amplifier circuit be located as close as possible to one another. Although it is possible to buy currentsensing resistors from established vendors (e.g., the LVR-1, -3 and -5 resistors from Dale), it is also possible to make a sense resistor using a short piece of wire or even a trace on a PC board.
Figures 30 and 31 illustrate the response of the overall isolation amplifier circuit shown in Figure 26. Figure 30 shows the response of the circuit to a 200 mV 20 kHz sine wave input and Figure 31 the response of the circuit to a 200 mV 20 kHz square wave input. Both figures demonstrate the fast, well-behaved response of the HCPL-7800. Figure 32 shows how quickly the isolation amplifier recovers from an overdrive condition generated by a 2 kHz square wave swinging between 0 and 500 mV (note that
the time scale is different from the previous figures). The first wave form is the output of the application circuit with the filter capacitors removed to show the actual response of the isolation amplifier. The second wave form is the response of the same circuit with the capacitors installed. The recovery time and overshoot are relatively independent of the amplitude and polarity of the overdrive signal, as well as its duration. For more information, refer to Application Note 1059.
VOLTAGE REGULATOR
CLOCK GENERATOR ISOLATION BOUNDARY
VOLTAGE REGULATOR
ISO-AMP INPUT
MODULATOR
ENCODER
LED DRIVE CIRCUIT
DETECTOR CIRCUIT
DECODER AND D/A
FILTER
ISO-AMP OUTPUT
Figure 28. HCPL-7800 Block Diagram.
Figure 29. PC Board Trace Pattern and Loading Diagram Example.
1-231
OPTOCOUPLERS
Figure 30. Application Circuit Sine Wave Response.
Figure 31. Application Circuit Square Wave Response.
Figure 32. Application Circuit Overload Recovery Waveform.
1-232

▲Up To Search▲

Price & Availability of HPCL7800

	To Download HPCL7800 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .